Plants generating renewable energy can be considered key components in the next generation of power systems, such as smart grids and microgrids. As discussed in the document by B. Burger and D. Kranzer titled “Extreme High Efficiency PV-Power Converter,” in Proc. EPE09, September 2009, these plants can also provide an alternate power source to known energy sources, such as oil, coal and natural gas.
A known characteristic for a renewable energy generating process is that an inverter is used in the process as an interface transforming available renewable energy in the form of a DC voltage to an AC voltage. Thus, DC/AC inverter technology can have a role in generating renewable energy in high power three-phase grid-connected applications.
DC/AC inverting technology can be implemented in various ways. The DC/AC inverting technology can have multiple degrees of freedom, for example, with respect to circuit topology, semiconductors, storage and filtering passive devices. These aspects can be interrelated, that is, changing one aspect can affect another. An effect of a change can manifest itself as an advantage or a drawback. Different combinations of different aspects can be used for serving different purposes.
A known approach for inverting a DC voltage into a three-phase AC voltage is to use a voltage source inverter (VSI), as renewable energy sources can be seen as DC voltage sources. If a DC voltage source can provide a sufficiently high voltage, only one power stage can be enough for the DC/AC conversion.
FIG. 1 shows a known two-level voltage source inverter with six switches S1 to S6. An advantage of this inverter topology is a smaller component count compared with some other topologies. However, the six switches S1 to S6 can have to be high-frequency semiconductors, and their breakdown characteristics should be such that the switches are able to handle the full DC link voltage. Because of high switching losses on the semiconductors, the known two-level voltage source inverter topology cannot always be suitable for applications with high switching frequency.
As discussed in U.S. Pat. No. 4,670,828, multi-level voltage source inverters were proposed to tackle the high switching losses of the two-level voltage source inverters. Output inductors of multi-level VSIs can be subjected to smaller transients, as the output voltage/current can be formed in smaller steps. This allows the use of output inductors with smaller inductances. Smaller inductances allow considerable reductions in size and losses of the inductors. FIGS. 2a to 2c show known three-level voltage source inverter topologies which have been adopted in industry and discussed in U.S. Pat. No. 7,126,409 B2, U.S. Patent Application Publication No. US 2009/0244936 A1, and U.S. Patent Application Publication No. US 2009/0003024 A1.
FIG. 2a illustrates a neutral-point-champed (NPC) voltage source inverter topology. In three-level topology, three inverter legs are implemented by using twelve switches S1 to S12. The inverter legs are clamped to the neutral point through diodes D1 to D6. Breakdown voltages of all semiconductors S1 to S12 and D1 to D6 are half of the DC link voltage. Thus, the switching losses of the semiconductors can be lower than those of a two-level voltage source inverter. Further, fast semiconductors can be utilized in the outer switches S1 to S3 and S10 to S12 and NPC diodes D1 to D6. Size and losses of the output inductors can be reduced by increasing the switching frequency. A drawback of this topology is that the inner slower switching switches S4 to S9 have relatively high conduction losses.
FIG. 2b illustrates a flying capacitor (FC) voltage source inverter topology. The three-level topology includes fewer semiconductors than the inverter NPC topology of FIG. 2a. Instead of clamping diodes, three flying capacitors C1 to C3 are used. In comparison with the topology of FIG. 2a, all semiconductors have to be rated capable of fast switching, and, thus, overall switching losses can become higher than those of the NPC topology. Moreover, control complexity of the topology can also be higher, as controlling the voltages of the flying capacitors C1 to C3 can also be specified.
FIG. 2c illustrates a T-type NPC voltage source inverter topology. A three-level output is achieved by using a half bridge including six switches S1 to S6 in combination with active clamping. In FIG. 2c, the active clamping is implemented by using switches S7 to S12. In comparison with the NPC topology of FIG. 2a, the slow switches S7 to S12 in FIG. 2c have fewer conduction losses. On the other hand, the faster switching switches S1 to S6 in FIG. 2c should be able to tolerate full DC voltage, which can increase their switching losses.
Wide-band-gap (WBG) semiconductors, such as Gallium Nitride (GaN) and Silicon Carbide (SiC), can be used to reduce the switching losses of these switches. The WBG semiconductors can be, however, more expensive than pure Silicon (Si) devices. The topology of FIG. 2c would have six expensive WBG switches, which can be seen as a drawback to the topology.
Another approach for converting a DC voltage to a three-phase AC voltage is by means of a current source inverter (CSI). FIGS. 3a and 3b illustrate some current source inverter topologies.
FIG. 3a shows a known current source inverter topology as discussed in the document of B. Sahan, S. Araujo, C. Nöding, and P. Zacharias titled “Comparative Evaluation of Three-Phase Current Source Inverters for grid interfacing of distributed and renewable energy systems,” IEEE Trans. Power Electron., vol. 26, no. 8, 2304-2318, August 2011. The topology shares a drawback with the two-level VSI topology in FIG. 2a. That is, six pairs of fast and high-breakdown-voltage switches S1 to S6 and diodes D1 to D6 can be used in FIG. 3a. The semiconductor losses can be high, and a current through a DC link inductor L1 circulates all the time which can lead to high power losses in the DC link inductor L1.
FIG. 3b illustrates an indirect current source inverter (ICSI) topology introduced in the document of R. Raik, N. Mohan, M. Rogers, and A. Bulawka titled “A noval grid interface optimized for utility-scale applications of photovoltaic, wind-electric, and fuel-cell systems,” IEEE Trans. Power Del., vol. 10, no. 4, pp. 1920-1926, October 1995, and discussed in WO 2009073582 A2. The topology uses two fast switches S1 and S2 for shaping the current of inductors L1 and L2, and six slow switches S3 to S8 to reform the currents. A lossy and bulky three-phase transformer 31 is used to convert them to in-phase currents. Total Harmonic Distortion (THD) of the output current can be very poor.